Logic Synthesis Tool Gives Users A High Degree Of Control October 1998 Issue Published Date: October 01, 1998
Significant new synthesis technology is claimed to be incorporated into Version 5.0 of Synplify, a logic synthesis tool for programmable logic design. The tool includes a multi-level timing constraints management system, which is said to give designers a great deal of flexibility. Multi-level timing constraints are a benefit to FPGA designers in that they allow an optimized set of constraints to be passed along to place and route, resulting in faster time-to-market. The tool's Synthesis Constraints Optimization Environment (SCOPE) provides a single graphical entry and editing environment for three different categories of constraints. As a result, very specific directions may be given to synthesis and place-and-route tools without over-constraining place and route.
