Architectural Synthesis Methodology Boosts Design Reusability September 1999 Issue Published Date: September 01, 1999
The Architectural Synthesis Tool Kit allows the interactive synthesis of designs of 100,000 or more operations in half the time required for hand-coded HDL designs, it’s claimed. The tool kit is suited for the development of architecture-optimized, reusable designs and for the implementation of highly optimized SOCs. Included within the kit are a variety of add-ons to the firm’s ART Builder C-to-HDL translation software. The pairing completely eliminates the need to manually develop RT-level designs by providing a variety of automated paths from behavioral C-language models to RT-level descriptions and by providing comprehensive analysis and optimization tools. Alpha tests of the tool kit have typically taken half as much time as previously required to hand-code them in Verilog or VHDL. Modifications of existing designs for re-use have been completed in one-third the time.
