VHDL/Verilog Simulator Shows 300% Speed Improvement July 2001 Issue Published Date: July 01, 2001
The new Active-HDL 4.2 Standard Edition shows a 300% simulation speed improvement over the previous 4.1 version for both VHDL and Verilog designs. Additionally, for Verilog designs, Active-HDL 4.2 includes memory resource allocation. Since VITAL libraries are built directly into Active-HDL, the speed of post place and route simulations is significantly increased. Version 4.2 equips designers with a powerful design and verification environment with separate stand-alone compilers and simulation engines for VHDL, Verilog and mixed VHDL, Verilog and EDIF verification. Mixed simulation gives designers the freedom to combine design styles and preferences, as well as enabling them to utilize IP Core technology for high-density, complex system-on-a-chip designs. The first year of maintenance is included in the product price of $3,600.00.
