Ultra High Speed DDR SDRAMs Launched November 2003 Issue Published Date: November 19, 2003
High-speed networking, video imaging and server cache are among the applications expected to tap the ultra high performance capabilities of a new family of memories now available for sampling. The reduced latency DRAM II devices combine fast random access with extremely high bandwidth and high density. Employing an eight-bank architecture, the 288-Mb RLDRAM II devices are said to achieve a peak bandwidth of 28.8 Gb/s using a 36-bit interface and a 400-MHz system clock. They also boast of a low latency and random cycle time of 20 ns. Other advantages of RLDRAM II include on-die termination (ODT), multiplexed or non-multiplexed addressing, on-chip delay lock loop (DLL), common and separate I/O, programmable output impedance, and a power efficient 1.8V core. These features are said to provide a memory that fully optimizes bus utilization whether the data bus is unidirectional or has a balanced read and write. For prices call MICRONTECHNOLOGY INC., Boise, ID. (208) 368-4400.
