IP Platform Reduces Static And Dynamic Power Dissipation July 2004 Issue Published Date: July 07, 2004
Promising static and dynamic power dissipation reductions up to 20x and 80%, respectively, the IPrima Mobile application-optimized semiconductor IP platform provides a wide range of power-management techniques. These include full block-level voltage islands, clock gating, mixed-transistor threshold voltage support, voltage frequency scaling, back biasing, and state retention standby mode. The platform contains single- and dual-port area, speed, and power (ASAP) SRAMs, single- and dual-port self-test and repair (STAR) SRAMs, single- and dual-port register files, and ROM. In addition, it employs the company's ultra-low-power (ULP) Standard Cell Library, which is based on the patented ASAP routing methodology and cell architecture and the ultra-high-density (UHD) Standard Cell set. For more information, call VIRAGE LOGIC CORP., Fremont, CA. (877) 360-6690.
