Software Eases DSP And FPGA Melding January 2005 Issue Published Date: January 19, 2005
For implementing DSP designs within FPGAs, Synplify DSP software allows users of the Simulink design environment from MathWorks to automatically take designs specified at the algorithm level and generate synthesis-ready RTL code. Via unique system-level optimizations, the application is said to produce circuits that are up to 50% faster and 30% smaller when compared to similar software tools. In addition to generating RTL code, the software also produces a test bench that can save time during the verification process. The generated RTL model can then be verified in any HDL simulator using the stimulus from the Simulink environment. The result is a single-source verification methodology from system model to gates. Pricing starts at $29,000 for a one-year, time-based license. SYNPLICITY INC., Sunnyvale, CA. (408) 215-6000.
