Synapticad Simulator Significantly Reduces Debug Time January 04, 2007
The VeriLogger Extreme compiled-code Verilog 2001 simulator promises to significantly reduce simulation debug time and offers fast simulation of both RTL and gate-level simulations with SDF timing information. The application supports design libraries and design flows for all major ASIC and FPGA vendors including Actel, Altera, Atmel, LSI Logic, QuickLogic, and Xilinx. Included in the package, BugHunter Pro graphical debugger comes bundled with the company’s graphical Verilog/VHDL integrated development environment. BugHunter Pro supports debugging with all major HDL simulators and supports source-level debugging, a waveform compression engine for high-speed waveform dumping and viewing, and graphical test bench generation features for testing HDL models. It also supports importing and exporting simulation test vectors to Agilent and Tektronix pattern generators and logic analyzers. VeriLogger Extreme is available on Linux, Solaris, and Windows platforms. A perpetual Windows license sells for $4,000. SYNAPTICAD INC., Blacksburg, VA, (800) 804-7073.
