IP Core Accelerates FPGA Access To DDR2 SDRAM March 13, 2007
The company has announced what it is calling the industry’s first 533-Mb/s DDR2 SDRAM controller IP core supporting the LatticeECP2/ECP2M low-cost FPGA families, and the high-end LatticeSC FPGA family. The core interfaces seamlessly with industry-standard DDR2 SDRAM devices. It supports all DDR2 commands and also provides intelligent bank management to minimize active commands. The most common memory configurations are supported through a combination of variable address widths for different memory devices, programmable timing parameters, byte level writing through data mask signals, and burst termination. LATTICE SEMICONDUCTOR CORP., Hillsboro, OR. (503) 268-8000.
