Architecture Packs NOR, ORNAND And Quad Flash On Single Die April 03, 2007
EMBEDDED SYSTEMS CONFERENCE, San Jose, CA. - To enable feature phones and multimedia portables with higher performance and lower costs, the MirrorBit Eclipse architecture combines MirrorBit NOR, ORNAND, and quad flash memory on a single die. The architecture is compatible with existing chipsets, a feature that promises a cost savings of 30% or more on handset memory subsystems and faster times to market. It also forecasts improved performance such as fast application loading and boot times, fast image storage and retrieval, and reduced energy burden from the memory sub-system to extend battery life. The first silicon products are expected in the third quarter and the company plans to sample 65-nm MirrorBit Eclipse devices on 300-mm wafers later this year. Based on 2-bit per cell technology, the chips will have the ability to run code at the high speed of traditional NOR, while moving multimedia at very fast rates. SPANSION INC., Sunnyvale, CA. (866) 772-67466.
