Package-On-Package Memory Saves Space June 2007 Issue Published Date: March 01, 2007
To further reduce board space in mobile phones, the company's package-on-package (PoP) technology is a multi-chip packaging technique that stacks a high-density memory component on top of the processor so the two components assume a single footprint. Initial PoP offerings include 14 mm x 14 mm and 15 mm x15 mm packages. The 15-mm devices are compliant with the JEDEC standard and will support Marvell's PXA3xx family of application processors, as well as other JEDEC-compatible processors. The 14-mm packages are compatible with other popular processor configurations. In a cell phone PoP configuration, two BGA packages are stacked vertically. Available configurations include 512 Mb to 1 Gb of SDRAM and up to 2 Gb of NAND flash. Initial configurations of PoP technology are sampling now in 14 mm x 14 mm (152 ball) and 15 mm x 15 mm (160 ball) sizes with a 0.65-mm ball pitch. Package height depends upon the number of die. TOSHIBA AMERICA ELECTRONIC COMPONENTS INC., San Jose, CA. (408) 526-2400.
