Clock Buffers Support Per-Channel Enable Controls July 28, 2008
Forecasting power, size, cost, and complexity reductions, the company’s latest clock-distribution ICs lay claim to being the first to provide per-channel output-enable controls. The two-channel STCD1020, three-channel STCD1030, and four-channel STCD1040 distribute a single master clock to multiple clock domains, allowing users to eliminate multiple crystal clocks for chipsets supporting GSM, Bluetooth, WLAN, WiMAX, and set-top boxes. Typical quiescent current is 2.6 mA and standby current is 1 uA for the STCD1040. From receipt of an enable signal, the selected channel’s output stabilizes within 50 ?s from standby. Reportedly, the STCD1040 draws 30% less current than a discrete four-channel topology requiring five emitter-follower circuits and typically occupies over 60% more PCB area. For transmission of a single-ended sine or square wave in the range 10 MHz to 52 MHz, the clock buffers also integrate an ac-coupling capacitor and they are capable of driving loads up to 20 pF. Standard supply voltage is 2.5V to 3.6V while the option of 1.65V to 2.75V allows for low-voltage peripherals. Price for the STCD1040 is $0.80 each/10,000. STMICROELECTRONICS, Lexington, MA. (888) 787-3550.
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