Clock ICs Break 100 Femtosecond Jitter Barrier August 01, 2008
Announced as the industry’s first clock synthesizer ICs to break the 100 femtosecond (fs) jitter barrier, the QuietClock family of clock synthesizers includes 25 sole source and second source clock devices with single-ended and differential outputs. They typically limit RMS jitter to 60 fs and cover the most popular frequencies common to PHY, MAC, SERDES, and memory subsystems. The family provides 3.3 V and 2.5 V operation, one to 10 outputs from a mix of single ended (LVCMOS) and differential (LVPECL and LVDS) outputs, and supports an industrial temperature range. It includes second source, pin-for-pin replacements for industry standard clocks encompassing the 840001/2/4/51, 9229/30, 12429/30, 843001/11/21/22, and 844001/21. The MQC1A0110 1:10 buffer provides functional compatibility with the industry standard 3807 buffer but with twice the frequency range; 1 MHz to 400 Mhz. Common applications for the QuietClock family include Gigabit Ethernet (GBE), serial Rapid I/O, SONET/SDH, Fibre Channel, Infiniband, and SATA. Pricing starts each/1,000 units. MULTIGIG INC., Scotts Valley, CA. (831) 440-0600.
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