CTS Technology Trims Clock Power September 08, 2008
After demonstrating a significant reduction in clock power while improving timing,
NXP Semiconductor now employs Azuro’s PowerCentric clock-tree synthesis (CTS) and optimization technology. Power savings are a the result of adding new clock gates to the design without significantly impacting the total cell area. Reportedly, PowerCentric’s multi-mode clock balancing capability sharply reduces the time and effort necessary to implement clocks simultaneously across all modes. A highly automated process, it also produces a tree with significantly smaller insertion delays. Another benefit, the technology has the ability to optimize the setup and hold timing concurrently with CTS. For more details, call AZURO INC., Santa Clara, CA. (408) 970-8200.
Electronic Design China 
