3G-SDI Dual SerDes Razes Jitter And Power Consumption September 11, 2008
Introduced as the industry’s first triple-rate (3G/HD/SD) serial digital interface, dual-channel serializer and deserializer transceiver, the LMH4345 promises to reduce board space, system cost, and power consumption in multi-channel broadcast video equipment. The transceiver delivers jitter spec of 30-ps output alignment jitter and 0.6 units interval minimum input jitter tolerance. Typical power consumption is 1.6W at data transmission rates of 3 Gb/s. The device supports 270 Mb/s, 1.485 Gb/s, and 2.97 Gb/s data rates. Its two receivers include a clock and data recovery circuit that automatically detects the incoming serial data rate, extracts the clock, and deserializes the data into a five-bit LVDS stream for interfacing with a host FPGA. Each transmitter includes an integrated, low-bandwidth PLL that cleans the parallel clock noise coming from the FPGA, eliminating the need for external clock conditioning. Available first quarter 2009 in a 100-pin, 14 mm x 14 mm TQFP, pricing is $55 each/100. NATIONAL SEMICONDUCTOR CORP., Santa Clara, CA. (800) 272-9959.
